In a power semiconductor device, a gate may be formed in a trench extending downward from the surface of a semiconductor silicon substrate, for example, a trench MOSFET a trench insulated gate bipolar transistor (IGBT) and the likes, which include various types of trench gates with different functions, but due to characteristics of the device structure itself, electric field intensity at the bottom of some trenches is at a highest level. When the voltage climbs to the avalanche breakdown point, impact ionization occurs at the corner of the trench resulting in the avalanche current. In general, the avalanche breakdown causes a hot carrier effect. When the breakdown occurs close to a gate oxide layer, an undesirable consequence is that the hot carrier may be captured and injected into the gate oxide layer, which may damage or break off the gate oxide layer, causing a long-term reliability problem of the power device. In addition, such trench often limits the device to achieve the high breakdown voltage.
In general, if the avalanche breakdown occurs during the low current levels, the performance of the device may not be significantly hampered when the breakdown occurs in a termination area, and there is no concern about the safety operation issues of the device. However, in some special operating periods, such as during an unclamped inductive switching (UIS) period, as the inductive current in a circuit system does not change suddenly, the device often bears certain higher voltage intensity, equivalently, when the device is in a high current avalanche breakdown stage the termination area with very limited surface area may not be able to handle the power loss safely and effectively because the active area of the power device cannot be reduced to increase the termination area, resulting the breakdown in the termination area becoming a negative effect on the safe operation area (SOA) of the device, which is undesirable. Particularly when the trench depth in the active area and the trench depth in the termination area is inconsistent, the terminal area will breakdown at a low voltage level.
In view of the prior art's problems, it is necessary to keep the device in the SOA at an optimal UIS condition to optimize the distribution of the electric field intensity of the power semiconductor device It is within this context that embodiments of the present invention arise.